The present invention relates to a method for fabricating a semiconductor device including self-aligned contacts.
In recent years, when contact members are formed to be interconnected to the source/drain regions of an MOS transistor, a self-aligned contact (SAC) structure is sometimes used to further increase the density of devices integrated on a chip. Specifically, in such a structure, a sidewall, which has been used for forming an LDD structure, is used again as an etch stopper for forming contacts in a self-aligned manner.
FIGS. 7(a) through 7(d) are cross-sectional views illustrating a conventional method for fabricating an MOS transistor with a known self-aligned contact structure. An LDD structure is often used recently for a transistor to meet the downsizing requirement. According to an ordinary method for fabricating such a transistor with an LDD structure, a sidewall is formed on a side of a gate electrode and heavily doped source/drain regions are formed by implanting ions into a substrate with that sidewall used as a mask.
First, in the process step shown in FIG. 7(a), a gate oxide film 102 (e.g., a thermal oxide film), a polysilicon film 103 for forming a gate electrode and a silicon nitride film 104 are formed in this order on a semiconductor substrate 101. And then a resist film 105 for patterning the gate is formed on the silicon nitride film 104.
Next, in the process step shown in FIG. 7(b), the silicon nitride film 104 and polysilicon film 103 are etched in this order using the resist film 105 as an etching mask, thereby forming an on-gate protective layer 104a and a gate electrode 103a. Thereafter, dopant ions are implanted into the semiconductor substrate 101 using the gate electrode 103a and the on-gate protective layer 104a as a mask, thereby forming lightly-doped source/drain regions 106. In this process step, phosphorus or arsenic ions are implanted to form an n-channel MOS transistor, or boron ions are implanted to form a p-channel MOS transistor. Then, a CVD oxide film 107 and a CVD nitride film 108 are deposited in this order over the substrate.
Subsequently, in the process step shown in FIG. 7(c), the CVD oxide film 107 and CVD nitride film 108 are dry-etched anisotropically to form an oxide sidewall 107a and a nitride sidewall 108a on a side of the gate electrode 103a. 
Thereafter, in the process step shown in FIG. 7(d), dopant ions are implanted into the semiconductor substrate 101 using the gate electrode 103a and the oxide and nitride sidewalls 107a and 108a as a mask, thereby forming heavily-doped source/drain regions 109. In this process step, phosphorus or arsenic ions are implanted to form an n-channel MOS transistor, or boron ions are implanted to form a p-channel MOS transistor. In this manner, an MOS transistor with an LDD structure is completed.
In a self-aligned contact structure, the nitride sidewall 108a formed in the above-described manner is used as an etch stopper in the process step of forming contact holes, thereby preventing the gate electrode from coming into electrical contact with the contact members.
FIG. 8 illustrates an exemplary cross section of an MOS transistor in which contact members have been formed. As shown in FIG. 8, an interlevel dielectric film 110 of silicon dioxide is deposited over the MOS transistor with the LDD structure shown in FIG. 7(d), and then planarized. Thereafter, contact holes are formed in the interlevel dielectric film 110 by photolithography and etching techniques so as to reach the heavily-doped source/drain regions 109. In this process step, even if part of a contact hole interferes with the on-gate protective layer 104a or the nitride sidewall 108a, the on-gate protective layer 104a or the nitride sidewall 108a is hardly etched. This is because the etch selectivity of the SiO2 interlevel dielectric film 110 to the SiN on-gate protective layer 104a or the nitride sidewall 108a is high. In other words, since the on-gate protective layer 104a and the nitride sidewall 108a serve as an etch stopper in the process step of forming contact holes, the gate electrode 103a can be protected. Thereafter, the contact holes are filled in with plug electrodes 111 and an interconnection layer (not shown) is formed thereon.
The nitride sidewall 108a is used not only as an ion implant mask for forming the heavily doped source/drain regions 109, but also as an etch stopper for protecting the gate electrode 103a in the process step of forming self-aligned contacts during the fabrication of an MOS transistor with SAC and LDD structures. However, it is already known that the direct contact of the nitride sidewall 108a with the side of the gate electrode 103a is likely to deteriorate the characteristics of the transistor. Thus, in the illustrated example, the thin oxide sidewall 107a is interposed between the gate electrode 103a and the nitride sidewall 108a. 
However, if a contact hole is formed to reach a region above the gate electrode 103a as shown in FIG. 8, then the upper edge of the oxide sidewall 107a is exposed inside the contact hole. And if that edge of the oxide sidewall 107a is etched away, then the resultant gap between the on-gate protective layer 104a and the nitride sidewall 108a is likely to be further removed. As a result, the contact hole might possibly reach the gate electrode 103a. That is to say, the plug electrode 111 as a contact member might be electrically short-circuited with the gate electrode 103a. 
To solve such a problem, the process steps shown in FIGS. 9(a) and 9(b) are carried out after the MOS transistor has been formed by performing the process steps shown in FIGS. 7(a) through 7(d). Specifically, the MOS transistor is covered with a relatively thick CVD nitride film 112, an interlevel dielectric film 110 is deposited over the entire surface of the substrate, and then contact holes are formed in the interlevel dielectric film 110. In such a case, the progress of etching is blocked by the CVD nitride film 112 by the time the contact hole has gone through the interlevel dielectric film 110 as shown in FIG. 9(b). Accordingly, it is possible to prevent the contact hole from reaching the gate electrode 103a with certainty.
The conventional process for fabricating a semiconductor device with an SAC structure, however, has the following drawbacks.
Specifically, if a relatively thick CVD nitride film 112 is deposited, then the gap between a pair of gate electrodes 103a for adjacent MOS transistors might be completely filled in with the CVD nitride film 112 as shown in FIG. 10. In general, since the gate length and pitch have recently been reduced to about 0.15 xcexcm and about 0.4 xcexcm, respectively, the gap between the gates is as small as approximately 0.25 xcexcm. In this particular LDD/SAC structure, the gap gets even smaller when taking the respective thicknesses of the oxide and nitride sidewalls into account. Accordingly, the gap is very likely to be totally filled in. In such a situation, it is virtually impossible to form such contact holes as reaching the source/drain regions 109 located under the gaps filled in with the CVD nitride film 112 as shown in FIG. 10. This is because other members might be adversely affected if such contact holes are provided.
An object of the present invention is providing a method for fabricating a semiconductor device, which functions as an MIS transistor with an SAC structure and can contribute to device miniaturization, by forming self-aligned contacts while improving the reliability thereof.
A method for fabricating a semiconductor device according to the present invention includes the steps of: a) forming a gate insulating film, a gate electrode and an on-gate protective layer in this order on a semiconductor substrate; b) implanting dopant ions into the semiconductor substrate using the gate electrode and the on-gate protective layer as a mask, thereby forming lightly-doped regions in the semiconductor substrate; c) depositing a first insulating film and a masking film in this order over the substrate, the masking film being able to be etched selectively with respect to the first insulating film; d) anisotropically etching the first insulating film and the masking film such that a first sidewall is formed on respective sides of the gate electrode and the on-gate protective layer by partially leaving the first insulating film thereon and that a second sidewall is formed on the first sidewall by partially leaving the masking film thereon; e) implanting dopant ions into the semiconductor substrate using the on-gate protective layer, the gate electrode and the first and second sidewalls as a mask, thereby forming heavily-doped regions in the semiconductor substrate; f) selectively removing the second sidewall so as to leave the first sidewall after the step e) has been performed; g) depositing a second insulating film over the substrate so as cover at least the on-gate protective layer and the first sidewall after the step f) has been performed; h) depositing an interlevel dielectric film over the substrate after the step g) has been performed, the interlevel dielectric film being made of a material that is able to be etched selectively with respect to the second insulating film; i) etching the interlevel dielectric film to form therein openings reaching the heavily-doped regions; and j) filling the openings in with plug electrodes made of a conductive material.
According to this method, since the second sidewall still exists in the step e), the heavily-doped regions can be formed in respective regions that are offset from the lightly-doped regions, thus obtaining an MIS transistor with a so-called LDD structure. On the other hand, since the second sidewall no longer exists in the step g), a sufficiently wide gap is ensured between a pair of gate electrodes of adjacent transistors. And it is possible to prevent the gap from being completely filled in with the second insulating film. Accordingly, a highly reliable, downsized semiconductor device with an SAC structure can be provided thanks to the existence of the second insulating film.
In one embodiment of the present invention, a Non-Doped Silicate Glass (NSG)film may be formed as the first insulating film and a PSG or BPSG film may be formed as the masking film in the step c).
In such an embodiment, a predetermined etch selectivity is ensured between the first and second sidewalls without causing any adverse effects such as a stress in the operating region of the semiconductor device.
In this particular embodiment, if the step f) is performed by HF vapor phase etching, only the second sidewall can be removed at a high etch selectivity.
In another embodiment, the method may further include the step of implanting dopant ions into the semiconductor substrate using the on-gate protective layer, the gate electrode and the first sidewall as a mask to form pocket implanted layers in the semiconductor substrate between the steps f) and g).
In such an embodiment, a semiconductor device can be formed with its punchthrough stop capability enhanced.
In still another embodiment, the method may further include, between the steps e) and f), the steps of: forming a protective film over the semiconductor substrate, the protective film being used as a mask for a non-silicide region; forming lightly-doped regions for preventing leakage under the heavily-doped regions using the protective film as a mask; selectively removing part of the protective film, which covers a silicide region, so as to leave the other part thereof covering the non-silicide region; and forming a silicide layer on the surface of the heavily-doped regions.
In such an embodiment, the lightly-doped regions for preventing leakage can be formed by using the protective film, which is also used as a mask for a silicidation process step. These lightly-doped regions for preventing leakage can reduce not only leakage current, but also junction capacitance. In addition, the silicide layer can reduce sheet resistance. As a result, the operating speed of the semiconductor device can be further increased.
A second method for fabricating a semiconductor device according to the present invention includes the steps of: a) forming a gate insulating film, a gate electrode and an on-gate protective layer in this order on a semiconductor substrate; b) depositing a first insulating film and a masking film in this order over the substrate, the masking film being able to be etched selectively with respect to the first insulating film; c) anisotropically etching the first insulating film and the masking film such that a first sidewall is formed on respective sides of the gate electrode and the on-gate protective layer by partially leaving the first insulating film thereon and that a second sidewall is formed on the first sidewall by partially leaving the masking film thereon; d) implanting dopant ions into the semiconductor substrate using the on-gate protective layer, the gate electrode and the first and second sidewalls as a mask, thereby forming heavily-doped regions in the semiconductor substrate; e) selectively removing the second sidewall so as to leave the first sidewall after the step d) has been performed; f) implanting dopant ions into the semiconductor substrate using the gate electrode, the on-gate protective layer and the first sidewall as a mask, thereby forming lightly-doped regions in the semiconductor substrate; g) depositing a second insulating film over the substrate so as cover at least the on-gate protective layer and the first sidewall after the step f) has been performed; h) depositing an interlevel dielectric film over the substrate after the step g) has been performed, the interlevel dielectric film being made of a material that is able to be etched selectively with respect to the second insulating film; i) etching the interlevel dielectric film to form therein openings reaching the heavily-doped regions; and j) filling the openings in with plug electrodes made of a conductive material.
According to the second method, the same effects as those attained by the first method are also attainable as a matter of principle. In addition, according to the second method, the lightly-doped regions are formed after the heavily-doped regions have been formed. Thus, annealing for activating the dopant in the heavily-doped regions can be conducted at a temperature high enough to increase the diffusion depth thereof sufficiently. As a result, the junction capacitance can be reduced. And at the same time, annealing for activating the dopant in the lightly-doped regions can be conducted at either a low temperature or a high temperature but for just a short period of time so as to suppress the short channel effects.
The same additional process steps as those of the first method are also applicable to the second method.